Supercomputers/Systems/Google TPU v4 supercomputer
USA · operational · ai training
Google TPU v4 supercomputer
Operated by Alphabet at Google Cloud (undisclosed location) .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
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- Rpeak
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- Rmax ÷ Rpeak
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- Cores
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- Power
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- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Accelerator | Google TPU v4 Accelerators 4096 chips interconnected by an internally-developed industry-leading optical circuit switch | Alphabet | 4,096 reported | Reported | cloud.google.comarxiv.org |
| Interconnect | Google TPU inter-chip interconnect (3D torus) Interconnect 3D torus · 1,200 GB/s bidirectional per chip (v5p and TPU7x) 3D torus interconnect with optical circuit switches | Alphabet | - | Reported | cloud.google.comarxiv.org |
AI datacenter metrics
Figures beyond an accelerator count, each with who stated it. What can and cannot be compared across AI datacenters.
| Metric | Value | As of | Basis | Note | Source |
|---|---|---|---|---|---|
| Accelerators | 4,096 accelerators | 2023-04 | Operator stated | Google blog (5 Apr 2023) and ISCA paper abstract: TPU v4 supercomputer of 4096 chips on optical circuit switches; both Google-authored | cloud.google.comarxiv.org |
The read
Google's TPU v4 machine of 4,096 chips joined by its own optical circuit switches, described in Google Cloud's April 2023 post and the ISCA 2023 paper by 14 Google authors, both of which say it has run since 2020. The blog, the paper and the Cloud documentation are all Google's, so the tier is reported. Google's blog shows one eighth of a pod in Oklahoma but that photograph does not establish where this system sits, so it stays at Google's undisclosed site and USA is only the operator's home country. Google's documentation gives per-chip peaks and a 1.1 exaflop pod peak in bf16 or int8; that is a vendor figure on a different basis from HPL, so no FLOPS are recorded. It never submitted an HPL result.
Site & facility
Change history
- 2026-09-20 Added Google's 4,096-chip TPU v4 supercomputer
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| arxiv.org | names system, part and count | Google TPU v4, Google TPU inter-chip interconnect (3D torus) · counts: 4096 |
| cloud.google.com | names system, part and count | Google TPU v4, Google TPU inter-chip interconnect (3D torus) · counts: 4096 |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.