Supercomputers/Systems/Google TPU 8i pod
USA · planned · ai inference
Google TPU 8i pod
Also known as TPU 8i Boardfly pod
Operated by Alphabet at Google Cloud (undisclosed location) .
Researched with AI assistance, checked by scripts. These rows were researched by AI agents reading public operator, laboratory and vendor sources, appended by scripts and checked by automated validation; no subject-matter expert has reviewed them (how this site is made). A mechanical second-reader pass has since fetched every cited source: 1350 of 1540 systems have a readable citation that names them, and 64 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
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- Rpeak
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- Rmax ÷ Rpeak
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- Cores
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- Power
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- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Accelerator | Google TPU 8i Accelerators TPU (systolic array) TPU 8i: 36 groups, up to 1,024 active chips in a Boardfly pod | Alphabet | 1,024 reported | Reported | cloud.google.com |
| CPU | - Arm-based Axion CPU headers across the TPU 8i system | Alphabet | - | Reported | cloud.google.com |
| Interconnect | - Boardfly topology: 4-chip trays, 8-board copper groups, 36 groups joined by optical circuit switches | Alphabet | - | Reported | cloud.google.com |
AI datacenter metrics
Figures beyond an accelerator count, each with who stated it. What can and cannot be compared across AI datacenters.
| Metric | Value | As of | Basis | Note | Source |
|---|---|---|---|---|---|
| Accelerators | 1,024 accelerators | 2026-04 | Design target | Google deep dive: up to 1,024 active chips in a TPU 8i pod (text also says up to 1,152 connected); no availability date given | cloud.google.com |
The read
The serving-and-reasoning eighth-generation Google TPU in its Boardfly pod, from the 22 April 2026 technical deep dive. Each TPU 8i has 288 GB of HBM at 8,601 GB/s, 384 MB of on-chip SRAM and 10.1 PFLOPS of FP4. The pod is built from 4-chip trays and 8-board copper-connected groups, with 36 groups joined by optical circuit switches for up to 1,024 active chips and a worst case of seven hops, against 16 hops for an 8x8x16 torus of the same size. The post says both 1,024 active chips and 'up to 1,152' connected chips; 36 x 8 x 4 = 1,152 raw, so the active count is recorded. No pod-level FLOPS, power or availability date is given (an interest form is offered), so the status is planned; the site is Google's undisclosed one and USA is the operator's home country. Sibling of google-tpu-8t-superpod.
Timeline
- 2026-04 Announced source
Site & facility
Change history
- 2026-10-17 Added Google TPU 8i 1,024-chip Boardfly pod (announced, no availability date)
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| cloud.google.com | names system, part and count | Google TPU 8i · counts: 1024 |
Checked 2026-10-18 by pnpm verify. Re-run it and the table changes with the web.