Supercomputers/Systems/Google TPU v5e pod
USA · operational · mixed
Google TPU v5e pod
Operated by Alphabet at Google Cloud (undisclosed location) .
Researched with AI assistance, checked by scripts. These rows were researched by AI agents reading public operator, laboratory and vendor sources, appended by scripts and checked by automated validation; no subject-matter expert has reviewed them (how this site is made). A mechanical second-reader pass has since fetched every cited source: 1350 of 1540 systems have a readable citation that names them, and 64 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
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- Rpeak
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- Rmax ÷ Rpeak
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- Cores
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- Power
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- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Accelerator | Google TPU v5e Accelerators TPU (systolic array) TPU v5e: 256 chips in a pod, 16x16 topology on 32 hosts | Alphabet | 256 reported | Reported | docs.cloud.google.com |
| Interconnect | - TPU inter-chip interconnect, 2D torus, 4 ICI ports per chip at 400 GBps bidirectional | Alphabet | - | Reported | docs.cloud.google.com |
AI datacenter metrics
Figures beyond an accelerator count, each with who stated it. What can and cannot be compared across AI datacenters.
| Metric | Value | As of | Basis | Note | Source |
|---|---|---|---|---|---|
| Accelerators | 256 accelerators | 2026-10 | Operator stated | Google Cloud docs: 256 chips per v5e pod; one documented pod configuration, not a site | docs.cloud.google.com |
The read
One Cloud TPU v5e pod in Google's documentation: 256 chips in a 16x16 2D torus across 32 hosts of eight chips, each chip 197 TFLOPs bf16 (393 TOPs int8) with 16 GB of HBM at 800 GiBps and 400 GBps of bidirectional inter-chip bandwidth over four ICI ports. Google lists 50.63 PFLOPs bf16 and 100 PetaOps int8 per pod; these are peak figures, not HPL, so no FLOPS is recorded. The largest training slice is the full 256 chips, while single-host serving slices stop at eight. Google documents it as a product configuration and does not say where pods are installed or how many exist, so the site is Google's undisclosed one and USA is the operator's home country. Undated documentation, so the status is as of the fetch date. Its successor is google-tpu-v6e-pod at about 4.7x the per-chip bf16.
Timeline
No dated events recorded.
Site & facility
Change history
- 2026-10-17 Added Google TPU v5e 256-chip pod (product configuration)
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| docs.cloud.google.com | names system, part and count | Google TPU v5e · counts: 256 |
Checked 2026-10-18 by pnpm verify. Re-run it and the table changes with the web.