Supercomputers/Systems/Google TPU 8t superpod
USA · planned · ai training
Google TPU 8t superpod
Also known as TPU 8t 9, 600-chip superpod
Operated by Alphabet at Google Cloud (undisclosed location) .
Researched with AI assistance, checked by scripts. These rows were researched by AI agents reading public operator, laboratory and vendor sources, appended by scripts and checked by automated validation; no subject-matter expert has reviewed them (how this site is made). A mechanical second-reader pass has since fetched every cited source: 1350 of 1540 systems have a readable citation that names them, and 64 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
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- Rpeak
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- Rmax ÷ Rpeak
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- Cores
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- Power
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- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Accelerator | Google TPU 8t Accelerators TPU (systolic array) TPU 8t: 9,600 chips in a single superpod | Alphabet | 9,600 reported | Reported | cloud.google.com |
| CPU | - Arm-based Axion CPU headers across the TPU 8t system | Alphabet | - | Reported | cloud.google.com |
| Interconnect | Google TPU inter-chip interconnect (3D torus) Interconnect 3D torus · 1,200 GB/s bidirectional per chip (v5p and TPU7x) 3D torus network topology at 9,600-chip scale, Virgo scale-out network between superpods | Alphabet | - | Reported | cloud.google.com |
AI datacenter metrics
Figures beyond an accelerator count, each with who stated it. What can and cannot be compared across AI datacenters.
| Metric | Value | As of | Basis | Note | Source |
|---|---|---|---|---|---|
| Accelerators | 9,600 accelerators | 2026-04 | Design target | Google deep dive: 9,600 chips in a single TPU 8t superpod; no availability date given | cloud.google.com |
The read
The training-oriented eighth-generation Google TPU in its 9,600-chip superpod configuration, from Google's technical deep dive of 22 April 2026. Each TPU 8t has 216 GB of HBM at 6,528 GB/s, 128 MB of on-chip SRAM and 12.6 PFLOPS of FP4; the superpod uses a 3D torus with Arm Axion CPU hosts, and the post claims 2x scale-up inter-chip bandwidth and up to 4x data-center-network bandwidth over the previous generation. Its Virgo scale-out network is said to link over 134,000 TPU 8t chips (47 Pb/s of bisection bandwidth) and Pathways to scale jobs beyond one million chips. The post gives no aggregate FLOPS or memory for a superpod, no power figure and no general-availability date (it offers an interest form), so the status is planned and no site is known; the site is Google's undisclosed one and USA is the operator's home country. Sibling of the inference-oriented google-tpu-8i-pod and successor to the Ironwood pod (google-tpu7x-pod).
Timeline
- 2026-04 Announced source
Site & facility
Change history
- 2026-10-17 Added Google TPU 8t 9,600-chip superpod (announced, no availability date)
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| cloud.google.com | names system, part and count | Google TPU 8t, Google TPU inter-chip interconnect (3D torus) · counts: 9600 |
Checked 2026-10-18 by pnpm verify. Re-run it and the table changes with the web.