Supercomputers/Systems/CEA-HE
France · operational · classified
CEA-HE
Also known as EXA1-HE
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- 90.79 PFlop/s
- Rpeak
- 171.3 PFlop/s
- Rmax ÷ Rpeak
- 53.0%
- Cores
- 548,352
- Power
- 1.77 MW
- Per watt
- 51.3 GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - Eviden BullSequana XH3000 | Eviden | - | Verified | top500.orgglobenewswire.com |
| Accelerator | NVIDIA GH200 Grace Hopper Superchip Accelerators Arm CPU + CUDA GPU · TSMC 4N 477 NVIDIA GH200 nodes | NVIDIA | - | Verified | top500.orgglobenewswire.com |
| CPU | NVIDIA Grace CPUs Armv9 (Neoverse V2) · 72C · 3.1 GHz · TSMC 4N NVIDIA Grace 72C 3GHz | NVIDIA | - | Reported | top500.org |
| Interconnect | Eviden BXI v2 Interconnect Fat tree or dragonfly+ · 100 Gb/s per port BXI, DragonFly topology, Quad-Rail BXI v2 | Eviden | - | Verified | einpresswire.comtop500.org |
| Cooling | Direct liquid cooling, warm water Cooling Direct-to-chip cold plates, facility water loop · Removes 90+ percent of node heat to liquid patented warm-water cooling system | Eviden | - | Reported | einpresswire.com |
The read
Phase 2 of CEA's EXA1 program, run by its Military Applications Division: NVIDIA GH200 superchips on Eviden's BullSequana XH3000, connected by BXI v2, Eviden's own DragonFly-topology fabric and one of the only interconnects in this dataset that is neither American nor Chinese. The joint CEA/Eviden release frames the machine around European sovereignty; the specific classified/nuclear-simulation framing traces to a press headline we could not directly fetch, so treat that characterization as reported rather than independently confirmed. CEA's own October 2025 slides describe 672 Grace Hopper nodes in 28 racks, while the Eviden release and TOP500 give 477; the two are not reconciled here and the 477 figure is kept.
Timeline
- 2024-04 Announced source
- 2024-06 List debut at #16 (June 2024) source
- 2024-06 First operational source
Public list appearances
Pointers only: rank and edition, linking to the canonical entry. We do not reproduce list tables. See sourcing policy.
Site & facility
Where sources disagree
We record conflicts instead of picking a winner quietly. All open questions.
- Grace Hopper node count: 477 nodes against 672 nodes in 28 racks. CEA's own October 2025 slides give the larger figure; the 477 is kept.
Change history
- 2026-09-22 Gained a Green500 rank pointer (#16 on the 2024-06 list)
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| top500.org | names system and part | NVIDIA GH200 Grace Hopper Superchip, NVIDIA Grace |
| globenewswire.com | names system and part | NVIDIA Grace, Eviden BXI v2, Direct liquid cooling, warm water |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Inside a node
Why accelerators exist, what the memory hierarchy costs, and how the CPU and accelerator merged onto one package.
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.