Supercomputers/Systems/Miyabi
Japan · operational · mixed
Miyabi
Operated by JCAHPC at JCAHPC (Miyabi) .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- 46.80 PFlop/s
- Rpeak
- 72.80 PFlop/s
- Rmax ÷ Rpeak
- 64.3%
- Cores
- 221,952
- Power
- 983.44 kW
- Per watt
- 47.6 GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Accelerator | NVIDIA GH200 Grace Hopper Superchip Accelerators Arm CPU + CUDA GPU · TSMC 4N Miyabi-G: 1,120 nodes each with one NVIDIA GH200 Grace Hopper | NVIDIA | 1,120 estimated | Reported | cc.u-tokyo.ac.jpjcahpc.jp |
| CPU | NVIDIA Grace CPUs Armv9 (Neoverse V2) · 72C · 3.1 GHz · TSMC 4N NVIDIA Grace 72-core CPU on each GH200 node | NVIDIA | - | Reported | cc.u-tokyo.ac.jpjcahpc.jp |
| Interconnect | NVIDIA InfiniBand NDR (Quantum-2) Interconnect Fat tree or dragonfly+ · 400 Gb/s per port · Under 0.6 microseconds InfiniBand NDR200, full-bisection fat tree | NVIDIA | - | Reported | cc.u-tokyo.ac.jp |
| Storage | DDN EXAScaler Storage Lustre appliance Lustre on DDN EXAScaler, 10 DDN ES400NVX2 servers | DDN | - | Reported | cc.u-tokyo.ac.jp |
AI datacenter metrics
Figures beyond an accelerator count, each with who stated it. What can and cannot be compared across AI datacenters.
| Metric | Value | As of | Basis | Note | Source |
|---|---|---|---|---|---|
| Accelerators | 1,120 accelerators | 2026-10 | Operator stated | U Tokyo: Miyabi-G has 1,120 compute nodes each equipped with a GH200 superchip (one GPU per node assumed from the platform). | cc.u-tokyo.ac.jp |
The read
The University of Tokyo and Tsukuba's joint system: 1,120 Grace Hopper nodes (Miyabi-G) and 190 Xeon Max nodes (Miyabi-C) on InfiniBand NDR200, with DDN Lustre storage. Figures are for Miyabi-G at its best TOP500 entry, 28th in November 2024; it has since slipped to 52nd. The University of Tokyo and Tsukuba describe the system, but their pages appear drawn from one source. No page we fetched names the city, so no coordinates are recorded. The GH200 count is one per node from the stated node count, so it is estimated.
Timeline
Public list appearances
Pointers only: rank and edition, linking to the canonical entry. We do not reproduce list tables. See sourcing policy.
Site & facility
Where sources disagree
We record conflicts instead of picking a winner quietly. All open questions.
- Storage capacity: 10.3 PB (JCAHPC) against 11.3 PB (University of Tokyo). No capacity is recorded.
Change history
- 2026-09-22 Gained a Green500 rank pointer (#33 on the 2024-11 list)
- 2026-09-20 Added with a rank pointer on the edition where it ranked highest
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| cc.u-tokyo.ac.jp | names system, part and count | NVIDIA GH200 Grace Hopper Superchip, NVIDIA Grace, NVIDIA InfiniBand NDR (Quantum-2) · counts: 1120 |
| top500.org | names system and part | NVIDIA Grace, NVIDIA InfiniBand NDR (Quantum-2) |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Inside a node
Why accelerators exist, what the memory hierarchy costs, and how the CPU and accelerator merged onto one package.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.
Storage and I/O
Parallel file systems, why checkpointing dominates the write load, and the metadata failure mode nobody expects.