Supercomputers/Systems/DeltaAI
USA · operational · ai training
DeltaAI
Operated by NCSA at NCSA National Petascale Computing Facility .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- -
- Rpeak
- -
- Rmax ÷ Rpeak
- -
- Cores
- -
- Power
- -
- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Accelerator | NVIDIA GH200 Grace Hopper Superchip Accelerators Arm CPU + CUDA GPU · TSMC 4N 152 nodes of four NVIDIA GH200 Grace Hopper superchips | NVIDIA | 608 reported | Reported | delta.ncsa.illinois.eduncsa.illinois.edu |
| CPU | NVIDIA Grace CPUs Armv9 (Neoverse V2) · 72C · 3.1 GHz · TSMC 4N NVIDIA Grace 72-core CPU on each GH200 | NVIDIA | - | Reported | delta.ncsa.illinois.edu |
| Interconnect | HPE Slingshot-11 Interconnect Dragonfly · 200 Gb/s per port · Around 2 microseconds HPE Slingshot 11, 200 Gb/s, one port per superchip | Hewlett Packard Enterprise | - | Reported | delta.ncsa.illinois.edu |
| Storage | VAST Data Platform Storage Disaggregated shared-everything Harbor (VAST) for home directories | VAST Data | - | Reported | delta.ncsa.illinois.edu |
AI datacenter metrics
Figures beyond an accelerator count, each with who stated it. What can and cannot be compared across AI datacenters.
| Metric | Value | As of | Basis | Note | Source |
|---|---|---|---|---|---|
| Accelerators | 608 accelerators | 2026-10 | Operator stated | NCSA: 608 NVIDIA GH200 superchips (H100 96GB GPUs). Both pages are NCSA, so not independent. | delta.ncsa.illinois.eduncsa.illinois.edu |
The read
NCSA's NSF-funded GPU system: 152 nodes of four NVIDIA GH200 superchips each, 608 in all, on Slingshot 11. NCSA is the only source, for both pages, so the tier is reported. The announcement and first-operational dates and any FLOPS figure are not on the pages we fetched. Green500's 2025-06 edition lists DeltaAI at rank 43, which means it also holds a TOP500 entry we have not independently pulled; its Rmax and TOP500 rank stay blank here until we fetch that page directly, but the ranked flag now reflects the Green500 pointer we do hold a source for.
Timeline
- 2025-06 List debut at #43 (June 2025) source
Public list appearances
Pointers only: rank and edition, linking to the canonical entry. We do not reproduce list tables. See sourcing policy.
Site & facility
NCSA National Petascale Computing Facility
- Location
- Urbana, IL, USA
- Cooling
- Chilled water
- Commissioned
- 2010
Change history
- 2026-09-22 Gained a Green500 rank pointer (#43 on the 2025-06 list)
- 2026-09-20 Added from operator sources
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| delta.ncsa.illinois.edu | names system, part and count | NVIDIA GH200 Grace Hopper Superchip, NVIDIA Grace, VAST Data Platform · counts: 608 |
| ncsa.illinois.edu | names system, part and count | NVIDIA GH200 Grace Hopper Superchip, NVIDIA Grace, VAST Data Platform · counts: 608 |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Inside a node
Why accelerators exist, what the memory hierarchy costs, and how the CPU and accelerator merged onto one package.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.
Storage and I/O
Parallel file systems, why checkpointing dominates the write load, and the metadata failure mode nobody expects.