Supercomputers/Systems/ROQUO
Japan · operational · mixed
ROQUO
Also known as JHPC-quantum GPU supercomputer
Operated by RIKEN at RIKEN Center for Computational Science .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- 19.80 PFlop/s
- Rpeak
- -
- Rmax ÷ Rpeak
- -
- Cores
- -
- Power
- -
- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - DTS Corporation built the system as primary builder | DTS Corporation | - | Reported | riken.jpr-ccs.riken.jp |
| Accelerator | - NVIDIA GB200 NVL4 Blackwell GPUs, 540 across 135 compute nodes | NVIDIA | 540 verified | Verified | riken.jpinvestor.nvidia.com |
| CPU | NVIDIA Grace CPUs Armv9 (Neoverse V2) · 72C · 3.1 GHz · TSMC 4N NVIDIA Grace CPUs, 270 in total | NVIDIA | 270 reported | Reported | riken.jp |
| Interconnect | NVIDIA InfiniBand XDR (Quantum-X800) Interconnect Fat tree or dragonfly+ · 800 Gb/s per port NVIDIA Quantum-X800 InfiniBand up to 3.2 Tb/s | NVIDIA | - | Verified | riken.jpinvestor.nvidia.com |
| Storage | - DataDirect Networks high-speed file system | DDN | - | Reported | riken.jp |
| Cooling | - warm-water free cooling with 32 C coolant | RIKEN | - | Reported | riken.jp |
AI datacenter metrics
Figures beyond an accelerator count, each with who stated it. What can and cannot be compared across AI datacenters.
| Metric | Value | As of | Basis | Note | Source |
|---|---|---|---|---|---|
| Accelerators | 540 accelerators | 2026-10 | Operator stated | 135 GB200 NVL4 nodes; RIKEN and NVIDIA agree on 540 Blackwell GPUs. | riken.jpinvestor.nvidia.com |
The read
RIKEN's GPU supercomputer for quantum-HPC hybrid research under the NEDO JHPC-quantum project, at the Kobe campus: 135 nodes of NVIDIA GB200 NVL4 with 540 Blackwell GPUs and 270 Grace CPUs on Quantum-X800 InfiniBand, 19.80 PFLOPS measured in HPL and warm-water free cooling with 32 C coolant. RIKEN names DTS Corporation as primary builder, Giga Computing Technology for node design and manufacture, ScaleWorX for integration and DataDirect Networks for the file system. Operation began on 19 June 2026. NVIDIA's November 2025 release independently gives the 540-GPU count. It has no TOP500 entry recorded here.
Site & facility
RIKEN Center for Computational Science
- Location
- Kobe, Japan
- Cooling
- Direct liquid cooling (warm water)
- Commissioned
- 2010
Change history
- 2026-10-07 Added ROQUO (RIKEN)
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| investor.nvidia.com | could not be fetched | - |
| riken.jp | names system, part and count | NVIDIA Grace, NVIDIA InfiniBand XDR (Quantum-X800) · counts: 270 |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
Inside a node
Why accelerators exist, what the memory hierarchy costs, and how the CPU and accelerator merged onto one package.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.