COMPUTE ATLAS Supercomputer supply-chain graph
1153 systems 482 sites Sourced data

Supercomputers/Systems/Bede

United Kingdom · operational · ai training

Bede

Also known as N8 Bede

Operated by N8 CIR .

Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.

Measured performance

Rmax
-
Rpeak
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Rmax ÷ Rpeak
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Cores
-
Power
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Per watt
- GF/W

Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.

What this machine is made of

One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.

Role Part Supplier at build Quantity Confidence Source
Integrator -
IBM Power AC922 (GPU) and IC922 (inference) nodes
IBM - Reported n8cir.org.ukdocs.hpc.shef.ac.uk
Accelerator NVIDIA Tesla V100
Accelerators
CUDA (Volta GV100) · 5,120C · 1.53 GHz · 12 nm · 300 W
NVIDIA V100, four per AC922 node on 32 nodes (arithmetic from node counts)
NVIDIA 128
estimated
Reported docs.hpc.shef.ac.ukn8cir.org.uk
Accelerator NVIDIA GH200 Grace Hopper Superchip
Accelerators
Arm CPU + CUDA GPU · TSMC 4N
NVIDIA GH200 Grace Hopper Superchips: seven single nodes plus one dual node (arithmetic from node counts)
NVIDIA 9
estimated
Reported docs.hpc.shef.ac.uk
CPU IBM POWER9 22C
CPUs
POWER · 22C · 3.07 GHz · 14 nm · 190 W
IBM POWER9, two CPUs per AC922 and IC922 node
IBM - Reported docs.hpc.shef.ac.ukn8cir.org.uk
Interconnect Mellanox InfiniBand EDR
Interconnect
Fat tree · 100 Gb/s per 4x port · About 0.9 microseconds
100 Gb/s EDR InfiniBand between nodes
NVIDIA - Reported docs.hpc.shef.ac.uk

The read

The N8 universities' EPSRC-funded Tier 2 GPU system, housed at Durham University and run by the N8 Centre of Excellence in Computationally Intensive Research. It reuses the Summit and Sierra architecture: 32 IBM AC922 nodes with two POWER9 CPUs and four NVIDIA V100 GPUs each, plus four IBM IC922 inference nodes with four T4 GPUs each. Since 2024 it also carries a Grace Hopper pilot: seven GH200 480GB nodes, one dual-GH200 node and a Grace login node (Sheffield's documentation counts these; the N8 page quoted three at the March 2024 start). Nodes use 100 Gb/s EDR InfiniBand, with NVLink within a node and a Lustre file system. The V100 and GH200 quantities in the parts table are our arithmetic from node counts. No commissioning date could be fetched and no TOP500 entry was found.

Timeline

No dated events recorded.

Change history

Source check

We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.

Cited sourceResultFound on the page
docs.hpc.shef.ac.uknames system, part and countIBM POWER9 22C, NVIDIA GH200 Grace Hopper Superchip, Mellanox InfiniBand EDR · counts: 9
n8cir.org.uknames system only · counts: 9

Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.

Further reading