Supercomputers/Systems/SAKURAONE
Japan · operational · ai training
SAKURAONE
Operated by SAKURA internet at SAKURA internet (Ishikari) .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- 33.95 PFlop/s
- Rpeak
- 47.79 PFlop/s
- Rmax ÷ Rpeak
- 71.0%
- Cores
- 115,248
- Power
- -
- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - Supermicro | Supermicro | - | Reported | top500.orgsakura.ad.jp |
| Accelerator | NVIDIA H100 SXM5 Accelerators CUDA (Hopper GH100) · 16,896C · 1.98 GHz · TSMC 4N · 700 W 100 nodes of eight NVIDIA H100 SXM 80GB | NVIDIA | 800 reported | Verified | arxiv.orgedge-core.com |
| Interconnect | Broadcom RoCE Ethernet Interconnect 800 GbE RoCEv2 leaf-spine, Broadcom Tomahawk 5 switch chips, ConnectX-7 NICs | Broadcom | - | Reported | arxiv.orgtop500.org |
| Storage | DDN EXAScaler Storage Lustre appliance DDN ES400NVX2 all-flash Lustre, 2 PB | DDN | - | Reported | arxiv.org |
AI datacenter metrics
Figures beyond an accelerator count, each with who stated it. What can and cannot be compared across AI datacenters.
| Metric | Value | As of | Basis | Note | Source |
|---|---|---|---|---|---|
| Accelerators | 800 accelerators | 2026-04 | Operator stated | 100 nodes x 8 H100 per the SAKURA internet Research Center paper. | arxiv.org |
The read
SAKURA internet's Supermicro cluster of 100 nodes with eight NVIDIA H100 GPUs each on an 800 GbE RoCE fabric of Edgecore white-box switches, sold as a managed cloud HPC service for large language model work. It was 49th on the June 2025 TOP500, its best rank, and slipped to 54th and then 69th. SAKURA and TOP500 agree on the 33.95 PFlop/s figure and the ranking. The operator's paper gives no start-of-service date and no power figure, and TOP500 lists none, so both are blank. The operator has since entered separate TOP500 rows named SAKURAONE CYB, CYC and CYD with newer GPUs, which are not recorded here. The Ishikari city comes from TOP500's site page for the operator, not from a page about this system.
Timeline
- 2025-06 List debut at #49 (June 2025) source
Public list appearances
Pointers only: rank and edition, linking to the canonical entry. We do not reproduce list tables. See sourcing policy.
Site & facility
Change history
- 2026-10-04 Added AI datacenter metrics for sakuraone
- 2026-09-20 Added with a rank pointer on the edition where it ranked highest
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| sakura.ad.jp | names system and part | NVIDIA H100 SXM5 |
| top500.org | names system, part and count | NVIDIA H100 SXM5 · counts: 800 |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
Inside a node
Why accelerators exist, what the memory hierarchy costs, and how the CPU and accelerator merged onto one package.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.