Supercomputers/Systems/Comet
USA · decommissioned · hpc
Comet
Operated by SDSC at San Diego Supercomputer Center .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- -
- Rpeak
- -
- Rmax ÷ Rpeak
- -
- Cores
- -
- Power
- -
- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - Dell-integrated cluster, 27 racks | Dell Technologies | - | Reported | sdsc.edusdsc.edu |
| Accelerator | NVIDIA Tesla P100 Accelerators CUDA (Pascal GP100) · 3,584C · 1.48 GHz · 16 nm · 300 W 36 nodes of four NVIDIA P100 added in 2017 | NVIDIA | 144 reported | Verified | sdsc.edutop500.org |
| Interconnect | Mellanox InfiniBand FDR Interconnect Fat tree · 56 Gb/s per 4x port · About 1 microsecond Mellanox FDR InfiniBand, full bisection per 72-node rack | Mellanox NVDANASDAQ
rolls up to NVIDIA | - | Verified | sdsc.edutop500.org |
The read
SDSC's NSF-funded Dell cluster of 1,944 dual-Haswell nodes on FDR InfiniBand, aimed at the long tail of science and the first XSEDE system with production virtualization. SDSC says early operations began in April 2015; 144 K80 GPUs were later joined by 144 P100s for 288 in all. SDSC and the NSF award record independently confirm the funding, but they disagree on the dollar figure, so none is recorded. SDSC planned to end service in March 2021, the NSF record runs to July 2021, and a later Globus post calls it officially retired, so only the year is recorded. We found no TOP500 entry for it, so there is no rank pointer, and SDSC's claims of 'more than two petaflops' against the NSF's 2.8 peak (with 48,784 cores against SDSC's 46,656 CPU cores) describe different eras, so no peak or core count is recorded.
Site & facility
Where sources disagree
We record conflicts instead of picking a winner quietly. All open questions.
- End of service: end of NSF service March 2021 (SDSC) against 75-month operating period to July 2021 (NSF award record). A later Globus post says Comet was retired by August 2021; only the year is recorded.
- NSF funding amount: $21.6 million (SDSC) against $27.3 million total, $12 million initial (NSF award record). The award grew through supplements; no figure is recorded.
Change history
- 2026-09-20 Added as an unranked NSF-funded system; end-of-service date disputed
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| api.nsf.gov | names system and part | Mellanox InfiniBand FDR |
| sdsc.edu | names system and part | Mellanox InfiniBand FDR |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.
Inside a node
Why accelerators exist, what the memory hierarchy costs, and how the CPU and accelerator merged onto one package.