Supercomputers/Systems/Quest (Northwestern)
USA · operational · mixed
Quest (Northwestern)
Also known as Northwestern Quest
Operated by Northwestern University .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- -
- Rpeak
- -
- Rmax ÷ Rpeak
- -
- Cores
- 80,000
- Power
- -
- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Accelerator | NVIDIA H100 SXM5 Accelerators CUDA (Hopper GH100) · 16,896C · 1.98 GHz · TSMC 4N · 700 W 24 nodes with four NVIDIA H100 80GB SXM5 GPUs each (Quest 13) | NVIDIA | 96 reported | Reported | it.northwestern.edu |
| Accelerator | NVIDIA A100 SXM4 80GB Accelerators 18 nodes with four NVIDIA A100 80GB SXM4 GPUs each (Quest 12) | NVIDIA | 72 reported | Reported | it.northwestern.edu |
| Accelerator | - 16 nodes with two NVIDIA A100 40GB PCIe GPUs each (Quest 10) | NVIDIA | 32 reported | Reported | it.northwestern.edu |
| Accelerator | - Further NVIDIA GPU cards on Priority Access nodes (269 total less the 200 General Access cards) | NVIDIA | 69 reported | Reported | it.northwestern.edu |
| Interconnect | NVIDIA InfiniBand NDR (Quantum-2) Interconnect Fat tree or dragonfly+ · 400 Gb/s per port · Under 0.6 microseconds InfiniBand NDR on the H100 nodes (Quest 13) | NVIDIA | - | Reported | it.northwestern.edu |
| Operating system | Red Hat Enterprise Linux Operating systems Linux distribution · Open source, commercial support subscription Red Hat Enterprise Linux 8.10 | Red Hat | - | Reported | it.northwestern.edu |
AI datacenter metrics
Figures beyond an accelerator count, each with who stated it. What can and cannot be compared across AI datacenters.
| Metric | Value | As of | Basis | Note | Source |
|---|---|---|---|---|---|
| Accelerators | 269 accelerators | 2026-10 | Operator stated | Page states 269 GPU cards on 91 GPU nodes across General Access and Priority Access. | it.northwestern.edu |
The read
Northwestern's shared HPC cluster. The specifications page states 7 login nodes and over 1,200 compute nodes with over 80,000 cores on Red Hat Enterprise Linux 8.10, including over 91 GPU nodes, and 269 GPU cards on 91 GPU nodes across General Access and Priority Access allocations. General Access GPU nodes are 24 Emerald Rapids nodes with four H100 SXM5 80 GB GPUs on NDR InfiniBand, 18 Ice Lake nodes with four A100 SXM4 80 GB GPUs on HDR, and 16 Cascade Lake nodes with two A100 40 GB PCIe GPUs (retiring fall 2026). No FLOPS figure is published.
Timeline
No dated events recorded.
Change history
- 2026-10-07 Added Quest (Northwestern)
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| it.northwestern.edu | names system, part and count | NVIDIA H100 SXM5, NVIDIA A100 SXM4 80GB, NVIDIA InfiniBand NDR (Quantum-2) · counts: 96 |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Inside a node
Why accelerators exist, what the memory hierarchy costs, and how the CPU and accelerator merged onto one package.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.
Programming a supercomputer
The software stack beneath the application, and why the OS is now a sovereignty signal as much as a technical choice.