Supercomputers/Systems/Peta4
United Kingdom · upgraded · hpc
Peta4
Also known as Cambridge Peta4
Operated by University of Cambridge at University of Cambridge (CSD3) .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- 1.70 PFlop/s
- Rpeak
- 2.88 PFlop/s
- Rmax ÷ Rpeak
- 59.0%
- Cores
- 46,464
- Power
- 479.76 kW
- Per watt
- 3.5 GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - Dell PowerEdge C6400 and C6320p nodes, co-designed with Dell EMC, Intel and NVIDIA | Dell Technologies | - | Reported | top500.orghelp.uis.cam.ac.uk |
| CPU | - Xeon Gold 6142 16C 2.6GHz Skylake plus Xeon Phi 7210 nodes | Intel | - | Reported | top500.orghelp.uis.cam.ac.uk |
| Interconnect | Omni-Path Architecture Interconnect Fat tree · 100 Gb/s per port · About 1 microsecond Intel Omni-Path interconnect (100Gbit/s) | Intel | - | Reported | top500.orghelp.uis.cam.ac.uk |
The read
CPU and Xeon Phi half of Cambridge's CSD3 service, co-designed with Dell EMC, Intel and NVIDIA with 9 million pounds of co-investment from the university, STFC and EPSRC. The 2019 University Information Services slides list 1,152 PowerEdge C6400 nodes with dual Xeon Gold 6142 CPUs (36,864 Skylake cores) and 342 C6320p nodes with Xeon Phi 7210 (21,888 KNL cores) on 100 Gbit/s Omni-Path, in production from November 2017 and upgraded in November 2018 and at Easter 2020. TOP500 lists the June 2018 entry at 46,464 cores, 1.70 PFLOPS Rmax, 2.88 PFLOPS peak and 479.76 kW, ranked 101st (76th in November 2017).
Timeline
Public list appearances
Pointers only: rank and edition, linking to the canonical entry. We do not reproduce list tables. See sourcing policy.
Site & facility
University of Cambridge (CSD3)
- Location
- Cambridge, United Kingdom
- Commissioned
- 2024
Change history
- 2026-10-02 Added Peta4, Cambridge's CSD3 CPU system
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| help.uis.cam.ac.uk | does not name this system | - |
| top500.org | names system and part | Omni-Path Architecture |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
Inside a node
Latency-optimised versus throughput-optimised processors, NUMA, and the end of the host-to-device copy.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.