Supercomputers/Systems/Redtail
USA · operational · ai training
Redtail
Also known as Utah AI Supercomputer
Operated by University of Utah .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- 12.85 PFlop/s
- Rpeak
- 13.63 PFlop/s
- Rmax ÷ Rpeak
- 94.3%
- Cores
- 38,544
- Power
- -
- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - 33 HPE Cray XD670 nodes | Hewlett Packard Enterprise | 33 reported | Reported | chpc.utah.edu |
| Accelerator | NVIDIA H200 SXM Accelerators CUDA (Hopper GH100) · 16,896C · 1.98 GHz · TSMC 4N · 700 W 264 NVIDIA H200 SXM5 GPUs, 141 GB each, 8 per node | NVIDIA | 264 reported | Reported | chpc.utah.edu |
| CPU | Intel Xeon Platinum 8570 CPUs x86-64 · 56C · 2.1 GHz · Intel 7 two Intel Xeon Platinum 8570 56-core CPUs per node (3,696 cores) | Intel | 66 reported | Reported | chpc.utah.edu |
| Interconnect | NVIDIA InfiniBand NDR (Quantum-2) Interconnect Fat tree or dragonfly+ · 400 Gb/s per port · Under 0.6 microseconds 400 Gb/s InfiniBand NDR with 24 switches in a rail-optimized fat tree | NVIDIA | - | Reported | chpc.utah.edu |
| Storage | WEKA Data Platform Storage Parallel filesystem, software-defined about 1 PB usable WEKA scratch | WEKA | - | Reported | chpc.utah.edu |
The read
The University of Utah's statewide AI supercomputer, an HPE Cray XD670 system operated by the Center for High Performance Computing (CHPC) and built through a roughly 50 million dollar public and private partnership with HPE, NVIDIA, the Huntsman Family Foundation and the State of Utah. CHPC's technical page lists 33 nodes with eight NVIDIA H200 SXM5 GPUs each (264 GPUs), two 56-core Intel Xeon Platinum 8570 CPUs per node (3,696 CPU cores), 2 TB DDR5 per node, 400 Gb/s NDR InfiniBand through 24 switches in a rail-optimized fat tree, and about 1 PB of usable WEKA scratch. The TOP500 site page for the University of Utah lists Redtail with 38,544 cores, 12.85 PFlop/s Rmax and 13.63 PFlop/s Rpeak. University of Utah news says it ranked 159th on the June 2026 TOP500 and 76th on the Green500; that edition is at its row cap in this dataset, so no list appearance is recorded and ranked stays 0. The data center location is not stated.
Timeline
No dated events recorded.
Change history
- 2026-10-02 Added Redtail, the University of Utah's AI supercomputer
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| chpc.utah.edu | names system, part and count | NVIDIA H200 SXM, Intel Xeon Platinum 8570, NVIDIA InfiniBand NDR (Quantum-2), WEKA Data Platform · counts: 264, 66 |
| top500.org | names system and part | NVIDIA H200 SXM, Intel Xeon Platinum 8570, NVIDIA InfiniBand NDR (Quantum-2) |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
Inside a node
Why accelerators exist, what the memory hierarchy costs, and how the CPU and accelerator merged onto one package.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.