Supercomputers/Systems/QUARTETTO
Japan · operational · hpc
QUARTETTO
Also known as Kyushu University QUARTETTO; HA8000-tc/HT210 and PRIMERGY CX400 cluster
Operated by RIIT, Kyushu University .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1263 of 1345 systems have a readable citation that names them, and 56 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- 1.02 PFlop/s
- Rpeak
- 1.50 PFlop/s
- Rmax ÷ Rpeak
- 67.8%
- Cores
- 222,072
- Power
- -
- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - Hitachi HA8000-tc/HT210 cluster of 965 nodes | Hitachi | - | Reported | hitachi.co.jptop500.org |
| Integrator | - Fujitsu PRIMERGY CX400 cluster portion | Fujitsu | - | Reported | top500.org |
| Accelerator | - Intel Xeon Phi 5110P coprocessors in the HT210 nodes | Intel | - | Reported | hitachi.co.jp |
| Accelerator | - NVIDIA K20 and K20x GPUs | NVIDIA | - | Reported | top500.org |
| CPU | Intel Xeon E5-2697 v2 CPUs x86-64 · 12C · 2.7 GHz · 22 nm · 130 W Intel Xeon E5-2697 v2 in the HT210 nodes | Intel | - | Reported | hitachi.co.jp |
| Interconnect | Mellanox InfiniBand FDR Interconnect Fat tree · 56 Gb/s per 4x port · About 1 microsecond InfiniBand FDR | Mellanox NVDANASDAQ
rolls up to NVIDIA | - | Reported | top500.org |
| Storage | - Hitachi Unified Storage 100 series, 4.1 PB | Hitachi | - | Reported | hitachi.co.jp |
The read
Kyushu University's Research Institute for Information Technology combined system, listed by TOP500 as QUARTETTO, a Hitachi HA8000-tc/HT210 plus Fujitsu PRIMERGY CX400 cluster with NVIDIA K20/K20x and Xeon Phi 5110P accelerators on FDR InfiniBand: 222,072 cores, 1,018 TFlop/s Rmax and 1,502.24 TFlop/s Rpeak, 37th in November 2013 and last listed 410th in November 2018 (https://top500.org/system/178251/). Hitachi's 31 January 2014 release says the HT210 part, 965 nodes with Xeon E5-2697 v2 and Xeon Phi 5110P, entered full operation on 27 December 2013, with a 720.6 TFlop/s aggregate theoretical performance for the new system and SR16000 VM1 servers beside it. The TOP500 power figure of 19,431 kW looks like a data-entry error and is not used. TOP500 lists an Xeon E5-2680 CPU where Hitachi names the E5-2697 v2, so the CPU rests on the operator. Reported. No site is recorded.
Timeline
Public list appearances
Pointers only: rank and edition, linking to the canonical entry. We do not reproduce list tables. See sourcing policy.
Change history
- 2026-10-09 Added QUARTETTO
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| hitachi.co.jp | does not name this system | Intel Xeon E5-2697 v2, Mellanox InfiniBand FDR |
| top500.org | names system and part | Intel Xeon E5-2697 v2, Mellanox InfiniBand FDR |
Checked 2026-10-13 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
Inside a node
Latency-optimised versus throughput-optimised processors, NUMA, and the end of the host-to-device copy.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.