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Parts/CPUs/AMD EPYC 9005 (Turin)

CPUs · Zen 5 · 2024

AMD EPYC 9005 (Turin)

Up to 192 Zen 5c cores, 12-channel DDR5. The 2025 default host CPU under an accelerator.

Why this part

Zen 5, and two distinct products under one name: up to 128 full Zen 5 cores for per-core performance, or up to 192 denser Zen 5c cores for throughput, in the same socket. The 2025 default host under an accelerator. Its 500W envelope is the clearest single number for why direct liquid cooling stopped being exotic: an air-cooled rack cannot carry eight of these plus eight GPUs.

Systems using this part

Systems
12
Rmax underneath
374.5 PFlop/s
Units recorded
1,536
2 of 12 edges disclose a quantity
System Role Country Units System Rmax Supplied by Rank
ASPIRE 2B (GPU Partition)
2026-06
CPU Singapore - 66.40 PFlop/s AMD #44 →
Roihu
2026-06
CPU Finland - - AMD -
ASPIRE 2B (CPU Partition)
2026-06
CPU Singapore - 10.09 PFlop/s AMD -
NIPA(NHN Cloud)-CL-1
2026-04
CPU South Korea - 137.4 PFlop/s AMD #20 →
NIPA(NHN Cloud)-CL-2
2026-04
CPU South Korea - 68.42 PFlop/s AMD #40 →
Teton
2026-01
CPU USA - 20.76 PFlop/s AMD #85 →
Cirrus
2025-12
CPU United Kingdom 512 4.12 PFlop/s AMD #314 →
NASA Athena
2025-12
CPU USA 1,024 15.98 PFlop/s AMD #116 →
PERUN
2025-11
CPU Slovakia - 10.21 PFlop/s AMD #162 →
Olivia
2025-06
CPU Norway - 13.20 PFlop/s AMD #134 →
PITAGORA
2024
CPU Italy - 27.90 PFlop/s AMD #44 →
Oxford ARC
CPU United Kingdom - - AMD -

“Units recorded” sums only the edges where a public source states a quantity. It is a floor, not a total, and should never be read as installed base.

Further reading