Supercomputers/Systems/Nautilus
USA · operational · mixed
Nautilus
Operated by Navy DSRC at Navy DSRC (Stennis Space Center) .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- 3.90 PFlop/s
- Rpeak
- 8.16 PFlop/s
- Rmax ÷ Rpeak
- 47.8%
- Cores
- 191,680
- Power
- -
- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - Penguin Computing TrueHPC | Penguin Computing | - | Reported | penguinsolutions.comtop500.org |
| Accelerator | - NVIDIA A100 (32 quad-GPU AI/ML nodes) plus 16 NVIDIA A40 visualization nodes | NVIDIA | - | Reported | penguinsolutions.comtop500.org |
| CPU | AMD EPYC 7713 (Milan) CPUs x86-64 · 64C · 2 GHz · 7 nm · 225 W AMD EPYC 7713 64C 2GHz (EPYC Milan, up to 128 cores per node) | AMD | - | Reported | top500.orgpenguinsolutions.com |
| Interconnect | NVIDIA InfiniBand HDR Interconnect Fat tree or dragonfly+ · 200 Gb/s per port · About 0.6 microseconds Infiniband HDR200 (200 Gbps NVIDIA Mellanox InfiniBand) | NVIDIA | - | Reported | top500.orgpenguinsolutions.com |
| Storage | - 26 PB DDN storage including 4.15 PB NVMe | DDN | - | Reported | penguinsolutions.com |
The read
Penguin Computing TrueHPC system at the US Navy DoD Supercomputing Resource Center at Stennis Space Center, Mississippi, part of the DoD HPCMP. Penguin's write-up describes 1,352 compute nodes of up to 128 AMD EPYC Milan cores each, 16 NVIDIA A40 visualization nodes, 32 quad-GPU NVIDIA A100 AI/ML nodes, a 200 Gbps NVIDIA Mellanox InfiniBand fabric and 26 PB of DDN storage (4.15 PB NVMe), with 8.2 petaFLOPS peak; it came out of a DoD contract awarded in September 2021 and completed final testing in April 2023. TOP500 lists AMD EPYC 7713 64C 2GHz, InfiniBand HDR200 and NVIDIA A100 with Rmax 3.90 PFlop/s, Rpeak 8.16 PFlop/s and 191,680 cores, first appearing on the November 2023 list at rank 194; the core counts differ between TOP500 (191,680) and the operator-side press figure (176,128 compute cores). The dataset uses TOP500 numbers, so the tier is reported.
Timeline
- 2021-09 Announced source
- 2023-04 First operational source
- 2023-11 List debut at #194 (November 2023) source
Public list appearances
Pointers only: rank and edition, linking to the canonical entry. We do not reproduce list tables. See sourcing policy.
Site & facility
Navy DSRC (Stennis Space Center)
- Location
- Stennis Space Center, MS, USA
Change history
- 2026-10-01 Added Nautilus (Navy DSRC)
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| top500.org | names system and part | AMD EPYC 7713 (Milan), NVIDIA InfiniBand HDR |
| penguinsolutions.com | names system and part | AMD EPYC 7713 (Milan), NVIDIA InfiniBand HDR |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
Inside a node
Latency-optimised versus throughput-optimised processors, NUMA, and the end of the host-to-device copy.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.