Supercomputers/Systems/Carina
USA · operational · ai training
Carina
Also known as CoreWeave Carina GB200 cluster
Operated by CoreWeave at CoreWeave (undisclosed US site) .
Researched with AI assistance, checked by scripts. These rows were researched by AI agents reading public operator, laboratory and vendor sources, appended by scripts and checked by automated validation; no subject-matter expert has reviewed them (how this site is made). A mechanical second-reader pass has since fetched every cited source: 1350 of 1540 systems have a readable citation that names them, and 64 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
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- Rpeak
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- Rmax ÷ Rpeak
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- Cores
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- Power
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- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - Carina built and delivered by CoreWeave for IBM, with NVIDIA technical expertise on the benchmark | CoreWeave | - | Reported | coreweave.cominvestors.coreweave.com |
| Accelerator | NVIDIA GB200 NVL72 Accelerators Arm CPU + CUDA GPU · TSMC 4NP 2,496 NVIDIA GB200 NVL72 Blackwell GPUs across 39 racks with 64 active GPUs each | NVIDIA | 2,496 reported | Reported | coreweave.cominvestors.coreweave.com |
| Interconnect | NVIDIA NVLink 5 / NVSwitch Interconnect All-to-all within an NVLink domain · 1.8 TB/s per GPU NVIDIA NVLink inside each GB200 NVL72 rack, used for rack-level job scheduling | NVIDIA | - | Reported | coreweave.com |
AI datacenter metrics
Figures beyond an accelerator count, each with who stated it. What can and cannot be compared across AI datacenters.
| Metric | Value | As of | Basis | Note | Source |
|---|---|---|---|---|---|
| Accelerators | 2,496 accelerators | 2025-06 | Operator stated | CoreWeave: 2,496 GB200 GPUs in the MLPerf Training v5.0 submission | coreweave.cominvestors.coreweave.com |
The read
CoreWeave's name for the 2,496-GPU NVIDIA GB200 NVL72 cluster that CoreWeave, NVIDIA and IBM entered in MLPerf Training v5.0, published 4 June 2025. CoreWeave's blog says it built and delivered Carina for IBM with NVIDIA's help on the benchmarking, so IBM is the customer and CoreWeave the operator of the infrastructure. It describes 39 racks with 64 GPUs active in each, which gives 39 x 64 = 2,496 (an NVL72 rack holds 72, so eight per rack sat idle in the run). The Llama 3.1 405B run finished in 27.33 minutes, which CoreWeave puts at 2.1x faster than NVIDIA's 2,560-GPU H100 entry, and it calls Carina one of the largest operational Blackwell clusters. NVIDIA's own v5.0 blog confirms a 2,496-GPU Blackwell submission but names neither CoreWeave nor Carina, and CoreWeave's press release repeats the GPU count without the name Carina. No page gives a location, so USA records CoreWeave's home country only. Compare coreweave-inflection-h100, CoreWeave's 3,584-GPU H100 MLPerf cluster from 2023.
Timeline
No dated events recorded.
Site & facility
Change history
- 2026-10-17 Added Carina, the CoreWeave 2,496-GPU GB200 cluster built for IBM (MLPerf Training v5.0)
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| coreweave.com | names system, part and count | NVIDIA GB200 NVL72, NVIDIA NVLink 5 / NVSwitch · counts: 2496 |
| investors.coreweave.com | could not be fetched | - |
Checked 2026-10-18 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Inside a node
Why accelerators exist, what the memory hierarchy costs, and how the CPU and accelerator merged onto one package.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.