Supercomputers/Systems/Laurel 2
Japan · operational · hpc
Laurel 2
Also known as Kyoto University System B (2016)
Operated by Kyoto University ACCMS .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- 821.90 TFlop/s
- Rpeak
- 1.03 PFlop/s
- Rmax ÷ Rpeak
- 79.9%
- Cores
- 30,600
- Power
- 357.11 kW
- Per watt
- 2.3 GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - Cray CS400 cluster supplied by Cray | Cray HPENYSE
rolls up to Hewlett Packard Enterprise | - | Reported | top500.orgintel.com |
| CPU | Intel Xeon E5-2695 v4 CPUs x86-64 · 18C · 2.1 GHz · 14 nm · 120 W Intel Xeon E5-2695 v4 18C 2.1GHz, 850 nodes with 2 processors each | Intel | 1,700 reported | Reported | top500.orgintel.com |
| Interconnect | Omni-Path Architecture Interconnect Fat tree · 100 Gb/s per port · About 1 microsecond Intel Omni-Path interconnect | Cornelis Networks | - | Reported | top500.org |
The read
Kyoto University's 2016 System B, a Cray CS400 of 850 two-socket Xeon E5-2695 v4 nodes (30,600 cores, 1.03 PFlop/s peak, 128 GB per node), sitting beside the Camphor 2 Cray XC40. Intel's customer story dates the installation to 2016, whereas the TOP500 lists installation year 2017 and a first appearance in June 2017. It was later superseded by Laurel 3.
Timeline
Public list appearances
Pointers only: rank and edition, linking to the canonical entry. We do not reproduce list tables. See sourcing policy.
Change history
- 2026-10-07 Added Laurel 2
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| intel.com | names system and part | Intel Xeon E5-2695 v4 |
| top500.org | names system and part | Intel Xeon E5-2695 v4, Omni-Path Architecture |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
Inside a node
Latency-optimised versus throughput-optimised processors, NUMA, and the end of the host-to-device copy.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.