Parts/CPUs/Fujitsu A64FX
Why this part
The most consequential design decision in the part is a subtraction: A64FX has no DDR interface at all. Every byte the processor sees comes from 32GB of on-package HBM2 at about 1 TB/s, roughly ten times the bandwidth per socket of a contemporary Xeon, and the tradeoff is that if your problem does not fit in 32GB per node it does not run. Fujitsu also moved off SPARC onto Arm and co-designed the SVE vector extension with Arm itself, which is how a Japanese national laboratory ended up steering a British instruction set. Fugaku ran 158,976 of them and led the list for two years without a single accelerator anywhere in the machine.
Systems using this part
- Systems
- 9
- Rmax underneath
- 517.8 PFlop/s
- Units recorded
- 438,704
| System | Role | Country | Units | System Rmax | Supplied by | Rank |
|---|---|---|---|---|---|---|
| Deucalion 2023-09 | CPU | Portugal | - | 3.96 PFlop/s | Fujitsu | #219 → |
| JMA PRIMEHPC FX1000 2023-03 | CPU | Japan | - | 13.37 PFlop/s | Fujitsu | #51 → |
| CWA FX1000 2023 | CPU | Taiwan | - | 11.16 PFlop/s | Fujitsu | #68 → |
| Wisteria/BDEC-01 2021-05 | CPU | Japan | - | 22.12 PFlop/s | Fujitsu | #99 → |
| TOKI-SORA 2020-11 | CPU | Japan | 276,480 | 16.59 PFlop/s | Fujitsu | #19 → |
| Flow 2020-07 | CPU | Japan | 2,304 | 6.62 PFlop/s | Fujitsu | #36 → |
| Fugaku 2020-06 | CPU | Japan | 158,976 | 442.0 PFlop/s | Fujitsu | #54 → |
| A64FX Prototype 2019 | CPU | Japan | 768 | 2.00 PFlop/s | Fujitsu | #6 → |
| Ookami | CPU | USA | 176 | - | Fujitsu | - |
“Units recorded” sums only the edges where a public source states a quantity. It is a floor, not a total, and should never be read as installed base.
Related news
- Fugaku takes the top position with no accelerators · RIKEN Center for Computational Science158,976 A64FX nodes, on-package HBM, and the Tofu fabric integrated onto the processor die. The shortest bill of materials of any modern leadership system.