Supercomputers/Systems/Sulis
United Kingdom · operational · hpc
Sulis
Also known as Sulis Tier 2
Operated by University of Warwick at University of Warwick (Sulis) .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- -
- Rpeak
- 1.80 PFlop/s
- Rmax ÷ Rpeak
- -
- Cores
- 28,244
- Power
- -
- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - Dell PowerEdge R6525 (CPU) and R7525 (GPU) nodes supplied by OCF | Dell Technologies | - | Reported | sulis-hpc.github.iowarwick.ac.uk |
| Accelerator | - 90 NVIDIA A100 40GB GPUs (30 nodes x 3) | NVIDIA | 90 reported | Reported | sulis-hpc.github.iowarwick.ac.uk |
| Accelerator | - 54 NVIDIA L40 48GB GPUs (18 nodes x 3) | NVIDIA | 54 reported | Reported | sulis-hpc.github.io |
| CPU | AMD EPYC 7742 (Rome) CPUs x86-64 · 64C · 2.25 GHz · 7 nm · 225 W AMD EPYC 7742 (Rome) 64-core on compute and A100 nodes; EPYC 7763 on L40 nodes; EPYC 7542 on very-high-memory nodes | AMD | - | Reported | sulis-hpc.github.io |
| Interconnect | NVIDIA InfiniBand HDR Interconnect Fat tree or dragonfly+ · 200 Gb/s per port · About 0.6 microseconds Mellanox ConnectX-6 HDR100 (100 Gbit/s) InfiniBand | NVIDIA | - | Reported | sulis-hpc.github.iowarwick.ac.uk |
| Storage | - IBM Spectrum Scale (GPFS) file system, 2.6 PB HDD and 800 TB SSD | IBM | - | Reported | sulis-hpc.github.io |
The read
The HPC Midlands+ Tier 2 service at the University of Warwick, funded with GBP 3 million from EPSRC, supplied by OCF on Dell PowerEdge servers and aimed at high-throughput and ensemble workflows for eight Midlands and London universities. Its technical page lists 167 CPU nodes and 4 high-memory plus 3 very-high-memory nodes on AMD EPYC Rome, 30 nodes with three A100 40GB GPUs each (90) and 18 nodes with three L40 48GB GPUs each (54), 28,244 CPU cores in total, Mellanox HDR100 InfiniBand and about 3.4 PB of IBM Spectrum Scale storage. Warwick's November 2021 launch release quoted 25,728 cores, 90 A100 GPUs and 1.8 double-precision PFlop/s; that peak figure predates the L40 and extra node additions, and no later peak was found. No TOP500 entry was found.
Timeline
- 2021-11 First operational source
Site & facility
University of Warwick (Sulis)
- Location
- Coventry, United Kingdom
- Commissioned
- 2021
Change history
- 2026-10-02 Added Sulis, the Warwick-hosted Midlands Tier 2 ensemble computing service
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| sulis-hpc.github.io | names system and part | AMD EPYC 7742 (Rome), NVIDIA InfiniBand HDR |
| warwick.ac.uk | names system and part | AMD EPYC 7742 (Rome), NVIDIA InfiniBand HDR |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
Inside a node
Latency-optimised versus throughput-optimised processors, NUMA, and the end of the host-to-device copy.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.