Supercomputers/Systems/Lynx (Arizona)
USA · planned · mixed
Lynx (Arizona)
Also known as UArizona Lynx
Operated by University of Arizona .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- -
- Rpeak
- -
- Rmax ÷ Rpeak
- -
- Cores
- 11,136
- Power
- -
- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - Lenovo V3 servers bought in 2026 | Lenovo | - | Reported | hpcdocs.hpc.arizona.edu |
| Accelerator | - 40 NVIDIA H200 GPUs, 8 per GPU node | NVIDIA | 40 reported | Reported | hpcdocs.hpc.arizona.edu |
| CPU | - AMD EPYC Turin 9655 and 9455 CPUs, 11,136 schedulable cores in total | AMD | - | Reported | hpcdocs.hpc.arizona.edu |
| Interconnect | NVIDIA InfiniBand NDR (Quantum-2) Interconnect Fat tree or dragonfly+ · 400 Gb/s per port · Under 0.6 microseconds NDR InfiniBand for MPI | NVIDIA | - | Reported | hpcdocs.hpc.arizona.edu |
AI datacenter metrics
Figures beyond an accelerator count, each with who stated it. What can and cannot be compared across AI datacenters.
| Metric | Value | As of | Basis | Note | Source |
|---|---|---|---|---|---|
| Accelerators | 40 accelerators | 2026-10 | Design target | Planned 40 NVIDIA H200 GPUs; the cluster is being acquired and is not yet available. | hpcdocs.hpc.arizona.edu |
The read
University of Arizona's next HPC cluster, which the research computing documentation says it is in the process of acquiring and which is not yet available. Planned hardware on that page: Lenovo V3 servers bought in 2026 with 55 CPU-only nodes, 5 GPU nodes and 1 high-memory node (11,136 cores in total, AMD EPYC Turin 9655 and 9455 CPUs), 40 NVIDIA H200 GPUs (eight per node), 41.4 TB of memory and NDR InfiniBand for MPI. The page says MIG partitioning of the H200s may be provisioned depending on test results. No FLOPS figure is published.
Timeline
No dated events recorded.
Change history
- 2026-10-07 Added Lynx (Arizona)
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
Every source cited on this page was readable, and none of them mentions this system. They are cited at page granularity, normally because no stable deep link could be found. That is a real weakness in this row and it is why the system carries a confidence tier below verified. See how this check works.
| Cited source | Result | Found on the page |
|---|---|---|
| hpcdocs.hpc.arizona.edu | does not name this system | - |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
Inside a node
Why accelerators exist, what the memory hierarchy costs, and how the CPU and accelerator merged onto one package.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.