Supercomputers/Systems/bwForCluster Helix
Germany · operational · mixed
bwForCluster Helix
Also known as Helix; bwForCluster Helix Heidelberg
Operated by Heidelberg University at Heidelberg University Computing Centre (URZ) .
Phase 1 seed dataset, compiled by hand. These rows were built from public operator, laboratory and vendor sources. A mechanical second-reader pass has since fetched every cited source: 1092 of 1153 systems have a readable citation that names them, and 40 are genuinely weakly sourced. Every claim carries its source and a confidence tier. Treat anything below verified as a lead, not a citation.
Measured performance
- Rmax
- -
- Rpeak
- -
- Rmax ÷ Rpeak
- -
- Cores
- -
- Power
- -
- Per watt
- - GF/W
Figures are as last publicly reported for the configuration described below, not a live measurement. Where a system was upgraded in place, the post-upgrade configuration is shown and the earlier one appears in the timeline.
What this machine is made of
One row per supplier relationship. “Supplier at build” is the company that shipped the part at the time; where that company has since been acquired, the parent it rolls up to today is shown beside it. That distinction is what makes ticker-level aggregation possible across a thirty-year dataset.
| Role | Part | Supplier at build | Quantity | Confidence | Source |
|---|---|---|---|---|---|
| Integrator | - MEGWARE computing cluster (storage supplied by ABC Systems) | MEGWARE | - | Reported | urz.uni-heidelberg.de |
| Accelerator | - NVIDIA A100, A40 and H200 GPUs: 55 four-GPU nodes and 7 eight-GPU nodes (about 200 Ampere GPUs at launch) | NVIDIA | - | Reported | wiki.bwhpc.deurz.uni-heidelberg.de |
| CPU | AMD EPYC 7513 (Milan) CPUs x86-64 · 32C · 2.6 GHz · 7 nm · 200 W 355 standard plus 15 fat nodes with two AMD EPYC 7513 (64 cores per node) (quantity is nodes) | AMD | 370 reported | Reported | wiki.bwhpc.deurz.uni-heidelberg.de |
| Interconnect | NVIDIA InfiniBand HDR Interconnect Fat tree or dragonfly+ · 200 Gb/s per port · About 0.6 microseconds Non-blocking NVIDIA Mellanox InfiniBand HDR, HDR100 on standard nodes up to 4x HDR200 on GPU nodes | NVIDIA | - | Reported | urz.uni-heidelberg.dewiki.bwhpc.de |
| Storage | - IBM Spectrum Scale (Storage Scale) file system, 11 PB with about 800 TB flash | IBM | - | Reported | urz.uni-heidelberg.dewiki.bwhpc.de |
The read
The state-level cluster for life sciences, natural sciences and computational humanities of Baden-Wuerttemberg, built by MEGWARE for Heidelberg University's computing centre (storage by ABC Systems) after a procurement that closed in June 2021, and live on 24 August 2022 as successor to bwForCluster MLS&WISO. Heidelberg describes about 20,000 AMD EPYC Milan cores, 100 TB of RAM, 200 NVIDIA Ampere GPUs (A100 and A40), non-blocking NVIDIA Mellanox InfiniBand HDR and 11 PB of IBM Spectrum Scale storage including 800 TB of flash. The bwHPC wiki now lists 355 standard and 15 fat nodes with two EPYC 7513 (64 cores per node), 55 four-GPU nodes with A40 or A100 and 7 eight-GPU nodes with A100 or H200, with interconnect from HDR100 to 4x HDR200. No HPL or peak figure is published in these sources, and the stated core count is approximate, so the cores field is blank.
Site & facility
Heidelberg University Computing Centre (URZ)
- Location
- Heidelberg, Germany
- Commissioned
- 2022
Change history
- 2026-10-04 Added bwForCluster Helix, Heidelberg
Source check
We fetched this system's own citations and recorded whether each page actually mentions it. This is a corroboration signal, not a fact check, and it is published so you can see how well the sourcing holds up rather than take it on trust.
| Cited source | Result | Found on the page |
|---|---|---|
| wiki.bwhpc.de | names system and part | AMD EPYC 7513 (Milan), NVIDIA InfiniBand HDR |
| urz.uni-heidelberg.de | names system and part | AMD EPYC 7513 (Milan), NVIDIA InfiniBand HDR |
Checked 2026-10-09 by pnpm verify. Re-run it and the table changes with the web.
Further reading
Operating a supercomputer
Acceptance testing, why "installed" and "in production" are six months apart, and the machine lifecycle.
Inside a node
Latency-optimised versus throughput-optimised processors, NUMA, and the end of the host-to-device copy.
The interconnect
Topologies, why latency and tail behaviour matter more than bandwidth, and how the fabric market consolidated.