Parts/Accelerators/Preferred Networks MN-Core (1st generation)
Accelerators · MN-Core 1 · 2018
Preferred Networks MN-Core (1st generation)
Deep-learning-specific ASIC co-developed by Preferred Networks and Kobe University: four dies per package, 2,048 Matrix Arithmetic Blocks, a SIMD grid with no conventional cache hierarchy or branch prediction. Peak 32.8 TFLOPS double precision, 131 TFLOPS single precision, roughly 500W per chip.
Why this part
It powered MN-3's four consecutive Green500 number-one rankings across 2020 and 2021, a rare non-GPU accelerator design at the top of that list, and the only accelerator vendor in this dataset that is neither NVIDIA, AMD nor a hyperscaler's own silicon.
Systems using this part
- Systems
- 1
- Rmax underneath
- 2.18 PFlop/s
- Units recorded
- 128
| System | Role | Country | Units | System Rmax | Supplied by | Rank |
|---|---|---|---|---|---|---|
| MN-3 2020-05 | Accelerator | Japan | 128 | 2.18 PFlop/s | Preferred Networks | #1 → |
“Units recorded” sums only the edges where a public source states a quantity. It is a floor, not a total, and should never be read as installed base.